1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a semiconductor device including a recess gate.
2. Description of Related Art
As semiconductor devices become highly integrated, a channel length of a cell transistor decreases. Furthermore, as an ion implantation doping concentration to a substrate increases, junction leakage also increases due to an increasing electric field. Thus, it may be difficult to secure a refresh characteristic of a semiconductor device with a typical planar type transistor structure.
Thus, a three-dimensional recess gate process is introduced to overcome the above limitations. According to the process, a portion of an active region in a substrate is etched to form a recess and a gate is formed over the recess. Thus, the channel length of the cell transistor increases and the ion implantation doping concentration to the substrate decreases, improving the refresh characteristic of the semiconductor device.
FIG. 1 illustrates a cross-sectional view of a method for fabricating a transistor including a typical recess gate. An isolation layer 12 is formed in a substrate 11 to define an active region. An oxide pattern 13 and a hard mask pattern 14 are formed over the substrate 11. The substrate 11 is partially etched using the hard mask pattern 14 as an etch mask to form recess regions having a vertical profile.
However, recently, as a semiconductor device becomes more highly integrated, a channel length of a cell transistor further decreases. Therefore, during employing the conventional method to form a recess region, the recess region may be formed with a V-shape profile. As a result, a horn may be formed on a substrate between an isolation layer and the recess region. That is, according to the conventional method employing a shallow trench isolation (STI) process for forming the isolation layer, the STI has an angle less than 90 degree in order for an insulation layer to gap-fill the trench. Meanwhile, the recess region has the V-shape profile because a pattern size decreases. Consequently, a large amount of residual silicon remains on the substrate after formation of the isolation layer and the recess region, forming the horn.
FIG. 2 illustrates a micrographic view of a profile of a typical recess pattern. The recess pattern has a V-shape profile and a horn A is generated on an interface between an isolation layer and a recess region. Since the recess pattern has the V-shape profile, the degree of residual silicon is large and thus, a height of the horn A is very high. Since the horn becomes a stress point causing a leakage current, a refresh characteristic and a production yield of the semiconductor device may be deteriorated.